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I am using Verilog mode, and after closing the port declarations parenthesis, emacs always inserts a space at the beginning of corresponding line .

To be more clear:

module ffff
(
    uuu,
    bla
 ); // <--- extra space added at the beginning of this line

wire   xxx;
reg    aaa;

endmodule

How can I avoid this annoying behaviour ?

simoxxxx
  • 1
  • I took a cursory look and I think this is caused by `verilog-calculate-indent`, but I didn't see any way to control that from the outside: you'd have to modify the code of `verilog-calculate-indent`. But maybe I missed something: caveat emptor. – NickD Apr 18 '23 at 14:34

0 Answers0