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I want to find out real RAM timings. The stick is 2400Mhz, but memory clock is limited to 2133MHz on this cpu. I can confirm it with:

$ sudo dmidecode
... 
Handle 0x0004, DMI type 17, 40 bytes
Memory Device
        Array Handle: 0x0003
        Error Information Handle: Not Provided
        Total Width: 64 bits
        Data Width: 64 bits
        Size: 8192 MB
        Form Factor: SODIMM
        Set: None
        Locator: ChannelA-DIMM0
        Bank Locator: BANK 0
        Type: DDR4
        Type Detail: Synchronous Unbuffered (Unregistered)
        Speed: 2133 MT/s
        Manufacturer: Samsung
        Asset Tag: None
        Part Number: M471A1K43BB1-CRC    
        Rank: 1
        Configured Memory Speed: 2133 MT/s
...

Checking current ram timings:

$ decode-dimms
# decode-dimms version $Revision$

Memory Serial Presence Detect Decoder
By Philip Edelbrock, Christian Zuckschwerdt, Burkart Lingner,
Jean Delvare, Trent Piepho and others


Decoding EEPROM: /sys/bus/i2c/drivers/ee1004/0-0050
Guessing DIMM is in                              bank 1


---=== SPD EEPROM Information ===---
EEPROM CRC of bytes 0-125                        OK (0xFE3E)


of bytes written to SDRAM EEPROM               384


Total number of bytes in EEPROM                  512
Fundamental Memory type                          DDR4 SDRAM
SPD Revision                                     1.1
Module Type                                      SO-DIMM
EEPROM CRC of bytes 128-253                      OK (0x55EF)


---=== Memory Characteristics ===---
Maximum module speed                             2400 MHz (PC4-19200)
Size                                             8192 MB
Banks x Rows x Columns x Bits                    16 x 16 x 10 x 64
SDRAM Device Width                               8 bits
Ranks                                            1
AA-RCD-RP-RAS (cycles)                           17-17-17-39
Supported CAS Latencies                          18T, 17T, 16T, 15T, 14T, 13T, 12T, 11T, 10T


---=== Timings at Standard Speeds ===---
AA-RCD-RP-RAS (cycles) as DDR4-2400              17-17-17-39
AA-RCD-RP-RAS (cycles) as DDR4-2133              15-15-15-35
AA-RCD-RP-RAS (cycles) as DDR4-1866              13-13-13-30
AA-RCD-RP-RAS (cycles) as DDR4-1600              11-11-11-26


---=== Timing Parameters ===---
Minimum Cycle Time (tCKmin)                      0.833 ns
Maximum Cycle Time (tCKmax)                      1.600 ns
Minimum CAS Latency Time (tAA)                   13.750 ns
Minimum RAS to CAS Delay (tRCD)                  13.750 ns
Minimum Row Precharge Delay (tRP)                13.750 ns
Minimum Active to Precharge Delay (tRAS)         32.000 ns
Minimum Active to Auto-Refresh Delay (tRC)       45.750 ns
Minimum Recovery Delay (tRFC1)                   350.000 ns
Minimum Recovery Delay (tRFC2)                   260.000 ns
Minimum Recovery Delay (tRFC4)                   160.000 ns
Minimum Four Activate Window Delay (tFAW)        21.000 ns
Minimum Row Active to Row Active Delay (tRRD_S)  3.300 ns
Minimum Row Active to Row Active Delay (tRRD_L)  4.900 ns
Minimum CAS to CAS Delay (tCCD_L)                5.000 ns
Minimum Write Recovery Time (tWR)                15.000 ns
Minimum Write to Read Time (tWTR_S)              2.500 ns
Minimum Write to Read Time (tWTR_L)              7.500 ns

Now, what does that mean? The clock is indeed 2133, that much I understand, but what are current timings? 17-17-17-39? 13-13-13-32? Neither of these matches "standard timing" of AA-RCD-RP-RAS (cycles) as DDR4-2133 15-15-15-35. Why is that?

1 Answers1

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The serial presence detect (SPD), which is read by decode-dimms, contains information about the module's general physical characteristics, but NOT its current operation mode. To check your current frequency configuration, access your BIOS and check out the configuration of your DRAM's frequency.

Depending on its frequency, the listed delays will be set in terms of "tCK", the period used internally in the DRAM (different from the bus frequency listed for the DIMM!). As an example, let's take tAA latency, 13.750ns. The minimum time for tAA in terms of "internal cycles" is 13.750ns/0.833ns = 16.5 cycles (0.833ns is the TCKmin, i.e. the minimum cycle time of the device); but there is no such thing as half a cycle, thus we must set AA safely to 17 cycles.
If our memory frequency is dubbed 2400 Mhz, we must first disregard the "double data rate", as its only good for bus transfers, and consider solely that the "period" (cycle time) of the bus is 1/1200Mhz (half of 2400) = 0.833ns (i.e. the tCKmin!). If we were to set our memory frequency lower, that would increase the period of the internal cycle. For instance, if we were to use 2133 Mhz, then the calculation becomes 13.750ns / 0.937ns = 14.67~, so we set AA to 15 cycles. At DDR 1866, 13.750ns / 1.071ns = 12.82, so we set AA to 13 cycles. At DDR 1600, 13.750ns / 1.25ns = 11, so we set AA to 11 cycles.

And those are precisely the timings shown for tAA in Timing Standard Speeds, represented as "cycles" of the device. You can repeat this exercise for other timings as well.

Francis Birck
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